Usually, two elements of a Base Station Subsystem (BSS) in a GSM network are connected via a synchronous PCM connection. The principle of such an STM connection (Synchronous Transfer Mode) is shown in FIG. 1A. One of the devices, i.e. a transmitter 1, is selected as a master and its clock is used to synchronize PCM frames sent over the connection. The second device, i.e. a receiver 2, has a slave function, since its own clock is synchronized to the master clock of the transmitter.
In future ATM based GSM networks, a transcoder (TC) and a Base Transceiver Station (BTS) are connected via an asynchronous ATM connection, wherein synchronization is not available at the receiver 2. In an ATM connection, bit streams of binary signals of different channels are divided into unitary ATM cells to be transmitted in a time divisional manner. The cell rate defines the total number of ATM cells per second.
FIG. 1B shows the principle of such an ATM connection, wherein a transmitting clock generator 3 and a receiving clock generator 4 are not synchronized and operate independently.
However, without a synchronization, the frequencies of the transmitting clock and the receiving clock are not equal. Therefore, a buffer of the receiver 2 may be filled gradually and a buffer overflow may occur, if the transmitting clock of the transmitter 1 is faster than the receiving clock of the receiver, since the buffer reading speed is slower than the writing speed. On the other hand, if the transmitting clock is slower than the receiving clock, the receiver 2 may run out of data (buffer underflow).
Both cases can result in lost data and, in case of time sensitive applications like GSM speech, cumulative delay that can rapidly become irritating. Thus, buffer underflow as well as buffer overflow is audible.
It is therefore an object of the present invention to provide a clock generating method and apparatus for an asynchronous transmission, by means of which clock synchronization between a transmitter and a receiver can be maintained.
This object is achieved by a clock generating method for an asynchronous transmission, comprising the steps of:                determining a plurality of actual signal arrival times;        averaging said plurality of actual signal arrival times; and        correcting a timing of a receiving clock on the basis of said average of the signal arrival times and an expected signal arrival time.        
Furthermore, the above object is achieved by a clock generating apparatus for an asynchronous transmission, comprising:                determining means for determining an average of actual signal arrival times and for generating a control signal on the basis of said average of the actual signal arrival times and an expected signal arrival time; and        correcting means for correcting a timing of a receiving clock on the basis of said control signal.        
Accordingly, since the timing of the receiving clock is corrected on the basis of an average of the actual arrival times of the signal and an expected arrival time, the receiving clock can be adjusted such that the expected arrival time coincides with the actual arrival time.
Moreover, by averaging the actual arrival time, delay variations upon signal transmission, which might cause synchronization errors, can be eliminated or at least significantly reduced.
Preferred developments of the present invention are defined in the subclaims.